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CDB8952
Crystal LAN? 10Base-T and 100Base-X Transceiver
Pins Function
1-2 Low Power Start
Description
The CS8952 will enter a low power mode following reset. Only the circuitry
necessary to maintain media impedance and the MII Serial Management
Interface will be operational. The CS8952 checks the status of these pins only
during power-on or reset. A reset or power cycle is required before any changes
in this jumper setting will take effect.
3-4
5-6
7-8
9-10
11-12
MII Receive Enable MII signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are tristated.
Power Down The CS8952 is forced into a low power mode. Only the circuitry necessary to
maintain media impedance will be operational.
CRS Mode Control The CRS pin will be asserted for receive activity only. The CS8952 checks the
status of these pins only during power-on or reset. A reset or power cycle is
required before any changes in this jumper setting will take effect.
Bypass Scrambler The scrambler and descrambler are bypassed, and NRZI FX mode is enabled.
The CS8952 checks the status of these pins only during power-on or reset. A
reset or power cycle is required before any changes in this jumper setting will
take effect.
Bypass 4B/5B Coders The 4B5B encoder and decoder are bypassed and 5-bit code groups are used.
RX_ER is used as the fifth receive bit, and TX_ER as the fifth transmit bit. The
CS8952 checks the status of these pins only during power-on or reset. A reset or
power cycle is required before any changes in this jumper setting will take effect.
13-14
Bypass Symbol
Alignment
4B5B coders, scramblers, and NRZI coders are all bypassed, and the CS8952
will make no attempt to identify code-group boundaries. Data on RXD[4:0] and
TXD[4:0] may contain bits from two code groups. The CS8952 checks the status
of these pins only during power-on or reset. A reset or power cycle is required
before any changes in this jumper setting will take effect.
15-16
17-18
19-20
Loopback The CS8952 will be placed in loopback mode. When operating in 100 Mb/s
mode, the loopback will be inside the PMD block, and scrambled NRZI data will
be routed directly to the NRZI input port on the descrambler. When in 10 Mb/s
mode, the CS8952 will perform a local ENDEC loopback.
MII Isolate The CS8952 will exit from reset with all MII signals tristated except MDIO and
MDC. The CS8952 checks the status of these pins only during power-on or reset.
A reset or power cycle is required before any changes in this jumper setting will
take effect.
10BASE-T Serial Mode If the CS8952 is in 10 Mb/s mode, data is transferred serially on RXD0 and
TXD0, and the full MII interface is disabled. When the CS8952 is in 100Mb/s
mode, shorting these pins has no effect. The CS8952 checks the status of these
pins only during power-on or reset. A reset or power cycle is required before any
changes in this jumper setting will take effect.
Table 6. Effect of shorting the listed pin pairs
HDR43
pins 1-2 shorted
open
pins 2-3 shorted
TX_CLK pin
input
input
output
CLK25 pin
25 MHz clock
not used
not used
LED Indicators
LED1 - Transmitter Active Indicator.
LED2 - Receiver Active Indicator.
Table 7. TX_CLK Mode Select
NOTE: When TX_CLK is an input, a shorting cap must
installed on HDR42 to supply TX_CLK to the
CS8952 (see HDR42).
LED3 - Link OK Indicator.
LED4 - Full Duplex Indicator.
LED5 - Collision Indicator.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
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